A pipeline analog-to-digital converter (ADC) generally includes a number of stages that are connected in a series configuration. The pipeline ADC 10 shown in FIG. 1 generally includes a stage 12, which provides an output signal that is input to the next stage 14, which in turn provides an output signal that is input to a following stage 16.
A 1.5 bits-per-stage architecture is a commonly used design for the pipeline ADC stages. Each stage can include a sub-ADC, a digital-to-analog converter (DAC), and a gain stage as shown FIG. 1. The sub-ADC 18 is connected to a DAC 20, which in turn provides an output that can be combined with the input 26 (whose value is referred to as VIN in FIG. 1). The resulting combination (see block 21) is applied as input to a gain stage 22, which provides an output (whose value is referred to as VOUT in FIG. 1).
The DAC and gain stage are often combined into a single common structure referred to as a multiplying digital-to-analog converter (MDAC). A single-ended switched-capacitor circuit implementation of the 1.5 bits-per-stage MDAC is depicted in FIG. 2 as circuit 30. As shown in FIG. 2, the circuit 30 generally includes an input 33 (whose value is referred to as VIN, and which is equivalent to VOUT from the previous stage) electrically connected to switches 32 and 34. Circuit 30 additionally includes a switch 36 that is electrically connected to the switch 34 and to a capacitor 40 (whose value is referred to as C2 in FIG. 2). The switch 32 is electrically connected to a capacitor 38 (whose value is referred to as C1 in FIG. 2) and to another switch 35. Both capacitors 38 and 40 are electrically connected to the inverting input of an amplifier 44. The non-inverting input of the amplifier 44 is electrically connected to a voltage 42 (whose value is referred to as VOS in FIG. 2), which in turn is connected to ground. The voltage 42 represents the offset voltage of the amplifier in the circuit 30. The output 46 of the amplifier (whose value is referred to as VOUT in FIG. 2, and is also equivalent to VIN for the next stage) is also connected to the switch 35.
Φ1 and Φ2 are two non-overlapping clocks. In FIG. 2, the switches 32 and 34 are closed when the clock Φ1 goes to a high value, while the switches 35 and 36 are closed when the clock Φ2 goes to a high value. The capacitor 38 can be considered as the feedback capacitor and the capacitor 40 can be regarded as the sampling capacitor. During the sampling phase, when Φ1 is high, the input signal VIN is sampled onto the bottom plates of the two capacitors 38 and 40. The charge stored on the capacitors at the end of the sampling phase is:QS=(C1+C2)(VIN−VOS)  [1]
During the next phase, called the amplification phase, when Φ2 is high, the capacitor 38 is switched into feedback around the amplifier and the bottom plate of the capacitor 40 is connected to a reference voltage whose value is referred to as VREF in FIG. 2. The charge stored on the capacitors at the end of the amplifying phase is:QAC1(VOUT−VOS)+C2(VREF−VOS)  [2]
Using the principle of charge conversion at the amplifier's inverting input,QS=QA  [3]
Therefore,
                              V          OUT                =                                            (                              1                +                                                      c                    2                                                        c                    1                                                              )                        ⁢                          V              IN                                -                                                    c                2                                            c                1                                      ⁢                          V              REF                                                          [        4        ]            
If both capacitors are equal valued, i.e., C1=C2=C, the above equation can be rewritten as:VOUT=2VIN−VREF  [5]
The above equation demonstrates that the amplifier's offset does not affect the functionality of the MDAC if the standard 1.5 bits-per-stage architecture is used as shown. However, to reduce power consumption in pipeline ADCs, the amplifier can be shared between adjacent stages and is used by a stage only during its amplification phase, as shown in FIG. 3.
FIG. 3 illustrates a schematic diagram of a 1.5 bits-per-stage MDAC circuit 51 that employs amplifier sharing between adjacent stages. Circuit 51 represents the stage during the sampling phase 52 and the amplification phase 60. The sampling phase 52 involves the use of capacitors 56 and 58, which are arranged in parallel to one another. The capacitors 56 and 58 are connected to ground and also to an input voltage whose value is referred to as VIN in FIG. 3. The input voltage is equivalent to the output voltage from the previous stage, whose value is referred to as VOUT. The amplification phase 60 includes an amplifier 68 in which the offset voltage 66 (whose value is referred to as VOS in FIG. 3) is applied to the non-inverting input terminal of the amplifier 60. A capacitor 62 is electrically connected to a reference voltage whose value is referred to as VREF and to the inverting input terminal of the amplifier 68 and further to a capacitor 64. The capacitor 64 is further tied to the output 70 (whose value is referred to as VOUT in FIG. 3) of the amplifier 68.
In reality, when the stage changes from the sampling phase 52 to the amplification phase 60, the capacitor 56 in the sampling phase becomes the capacitor 64 in the amplification phase. Therefore, the capacitors 56 and 64 are the same and their value is referred to as C1 in FIG. 3. Similarly, the capacitors 58 and 62 are the same and their value is referred to as C2 in FIG. 3.
During the sampling phase, the input voltage is sampled onto the capacitors 56 and 58. The charge stored on the capacitors at the end of the sampling phase is:QS=(C1+C2)VIN  [6]
During the amplification page, the amplifier is introduced into the circuit as shown in FIG. 3. The charge stored on the capacitors as the end of the amplifying phase is:QA=C1(VOUT−VOS)+C2(VREF−VOS)  [7]
Using the principle of charge conversion at the amplifier's inverting input terminal,QS=QA  [8]
Therefore,
                              V          OUT                =                                            (                              1                +                                                      C                    2                                                        C                    1                                                              )                        ⁢                          V              IN                                -                                                    C                2                                            C                1                                      ⁢                          d              i                        ⁢                          V              REF                                +                                    (                              1                +                                                      C                    2                                                        C                    1                                                              )                        ⁢                          V              OS                                                          [        9        ]            
If C1=C2=C, the above equation can be rewritten as:VOUT=2VIN−VREF+2VOS  [10]
The output voltage is now influenced by the amplifier's offset voltage. As the signal travels down the pipeline stages, the offset of the amplifier in each stage is similarly added along. This leads to a shift in the ADC's input-output transfer curve as shown in FIG. 4 and impacts applications where absolute conversion accuracy is required. FIG. 4 illustrates a graph 72 that represents data indicating shift in the input-output curve due to offset error in an ADC.